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general description the max1036?ax1039 low-power, 8-bit, multichannel, analog-to-digital converters (adcs) feature internal track/hold (t/h), voltage reference, clock, and an i 2 c-compatible 2-wire serial interface. these devices operate from a single supply and require only 350? at the maximum sampling rate of 188ksps. auto- shutdown powers down the devices between conver- sions reducing supply current to less than 1? at low throughput rates. the max1036/max1037 have four ana- log input channels each, while the max1038/max1039 have twelve analog input channels. the analog inputs are software configurable for unipolar or bipolar and single- ended or pseudo-differential operation. the full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1v to v dd . the max1037/ max1039 feature a 2.048v internal reference and the max1036/max1038 feature a 4.096v internal reference. the max1036/max1037 are available in 8-pin sot23 packages. the max1038/max1039 are available in 16- pin qsop packages. the max1036?ax1039 are guar- anteed over the extended industrial temperature range (-40? to +85?). refer to max1136?ax1139 for 10-bit devices and to the max1236?ax1239 for 12-bit devices. applications handheld portable applications medical instruments battery-powered test equipment solar-powered remote systems received-signal-strength indicators system supervision features high-speed i 2 c-compatible serial interface 400khz fast mode 1.7mhz high-speed mode single supply 2.7v to 3.6v (max1037/max1039) 4.5v to 5.5v (max1036/max1038) internal reference 2.048v (max1037/max1039) 4.096v (max1036/max1038) external reference: 1v to v dd internal clock 4-channel single-ended or 2-channel pseudo- differential (max1036/max1037) 12-channel single-ended or 6-channel pseudo- differential (max1038/max1039) internal fifo with channel-scan mode low power 350 a at 188ksps 110 a at 75ksps 8 a at 10ksps 1 a in power-down mode software configurable unipolar/bipolar small packages 8-pin sot23 (max1036/max1037) 16-pin qsop (max1038/max1039) max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ________________________________________________________________ maxim integrated products 1 ordering information/selector guide 19-2442; rev 4; 5/09 part pin-package tue (lsb) input channels i 2 c slave address internal reference (v) top mark max1036 eka+t 8 sot23 ? 4 1100100 4.096 aaje max1037 eka+t 8 sot23 ? 4 1100100 2.048 aajg max1038 aeee+ 16 qsop ? 12 1100101 4.096 max1039 aeee+ 16 qsop ? 12 1100101 2.048 autoshutdown is a trademark of maxim integrated products, inc. pin configurations and typical operating circuit appear at end of data sheet. evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim's website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel.
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 2.7v to 3.6v (max1037/max1039), v dd = 4.5v to 5.5v (max1036/max1038). external reference, v ref = 2.048v (max1037/max1039), v ref = 4.096v (max1036/max1038). external clock, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ain0?in11, ref to gnd ......................-0.3v to the lower of (v dd + 0.3v) and +6v sda, scl to gnd.....................................................-0.3v to +6v maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 8-pin sot23 (derate 7.1mw/? above +70?).............567mw 16-pin qsop (derate 8.3mw/? above +70?).........666.7mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 8 bits relative accuracy inl (note 2) 1 lsb differential nonlinearity dnl no missing codes over temperature 1 lsb offset error 1.5 lsb offset error temperature coefficient 3 ppm/ c gain error (note 3) 1 lsb gain temperature coefficient 1 ppm/ c max1036/max1037 0.5 2 total unadjusted error tue max1038a/max1039a 0.5 1 lsb channel-to-channel offset matching 0.1 lsb channel-to-channel gain matching 0.5 lsb input common-mode rejection ratio cmrr pseudo-differential input mode 75 db dynamic performance (f in ( sine wave ) = 25khz, v in = v ref ( p-p ) , f sample = 188ksps, r in = 100 ) signal-to-noise plus distortion sinad 49 db total harmonic distortion thd up to the 5th harmonic -69 db spurious-free dynamic range sfdr 69 db channel-to-channel crosstalk (note 4) 75 db full-power bandwidth -3db point 2.0 mhz full-linear bandwidth sinad > 49db 200 khz conversion rate internal clock 6.1 conversion time (note 5) t conv external clock 4.7 ?
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max1037/max1039), v dd = 4.5v to 5.5v (max1036/max1038). external reference, v ref = 2.048v (max1037/max1039), v ref = 4.096v (max1036/max1038). external clock, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units internal clock, scan[1:0] = 01 (max1036/max1037) 76 internal clock, scan[1:0] = 00 cs[3:0] = 1011 (max1038/max1039) 77 throughput rate f sample external clock 188 ksps track/hold acquisition time 588 ns internal clock frequency 2.25 mhz external clock, fast mode 45 aperture delay t ad external clock, high-speed mode 30 ns analog input (ain0?in11) unipolar 0 v ref input voltage range, single ended and differential (note 6) bipolar v ref / 2 v input multiplexer leakage current on/off-leakage current, v ain _= 0 or v dd, no clock, f scl = 0 0.01 1a input capacitance c in 18 pf internal reference (note 7) max1037/max1039 1.925 2.048 2.171 reference voltage v ref t a = +25? max1036/max1038 3.850 4.096 4.342 v reference temperature coefficient tc ref 120 ppm/ c reference short-circuit current 10 ma reference source impedance (note 8) 675 external reference reference input voltage range v ref (note 9) 1.0 v dd v ref input current i ref f sample = 188ksps 14 30 ? digital inputs/outputs (scl, sda) input high voltage v ih 0.7 x v dd v input low voltage v il 0.3 x v dd v input hysteresis v hyst 0.1 x v dd v input current i in v in = 0 to v dd 10 ? input capacitance c in 15 pf output low voltage v ol i sink = 3ma 0.4 v
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 2.7v to 3.6v (max1037/max1039), v dd = 4.5v to 5.5v (max1036/max1038). external reference, v ref = 2.048v (max1037/max1039), v ref = 4.096v (max1036/max1038). external clock, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units power requirements max1037/max1039 2.7 3.6 supply voltage (note 10) v dd max1036/max1038 4.5 5.5 v internal ref, external clock 350 650 f sample = 188ksps external ref, external clock 250 external ref, external clock 110 f sample = 75ksps external ref, internal clock 150 external ref, external clock 8 f sample = 10ksps external ref, internal clock 10 external ref, external clock 2 f sample = 1ksps external ref, internal clock 2.5 supply current i dd power-down 1 10 ? power-supply rejection ratio psrr (note 11) 0.25 1 lsb/v timing characteristics for 2-wire fast mode (figures 1a and 2) serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 ? hold time for start condition t hd , sta 0.6 ? low period of the scl clock t low 1.3 ? high period of the scl clock t high 0.6 ? setup time for a repeated start condition (sr) t su , sta 0.6 ? data hold time t hd , dat (note 12) 0 150 ns data setup time t su , dat 100 ns rise time of both sda and scl signals, receiving t r (note 13) 20 + 0.1c b 300 ns fall time of sda transmitting t f (note 13) 20 + 0.1c b 300 ns setup time for stop condition t su , sto 0.6 ? capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 50 ns timing characteristics for 2-wire high-speed mode (figures 1b and 2) serial clock frequency f sclh (note 14) 1.7 mhz hold time (repeated) start condition t hd , sta 160 ns low period of the scl clock t low 320 ns high period of the scl clock t high 120 ns
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max1037/max1039), v dd = 4.5v to 5.5v (max1036/max1038). external reference, v ref = 2.048v (max1037/max1039), v ref = 4.096v (max1036/max1038). external clock, f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units setup time for a repeated start condition (sr) t su , sta 160 ns data hold time t hd , dat (note 12) 0 150 ns data setup time t su , dat 10 ns rise time of scl signal (current source enabled) t rcl (note 13) 20 80 ns rise time of scl signal after acknowledge bit t rcl1 (note 13) 20 160 ns fall time of scl signal t fcl (note 13) 20 80 ns rise time of sda signal t rda (note 13) 20 160 ns fall time of sda signal t fda (note 13) 20 160 ns setup time for stop condition t su , sto 160 ns capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 010ns note 1: the max1036/max1038 are tested at v dd = 5v and the max1037/max1039 are tested at v dd = 3v. all devices are config- ured for unipolar, single-ended inputs. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. note 3: offset nulled. note 4: ground on channel; sine wave applied to all off channels. note 5: conversion time is defined as the number of clock cycles (8) multiplied by the clock period. conversion time does not include acquisition time. scl is the conversion clock in the external clock mode. note 6: the absolute voltage range for the analog inputs (ain0?in11) is from gnd to v dd . note 7: when ain_/ref is configured to be an internal reference (sel[2:1] = 11), decouple ain_/ref to gnd with a 0.01? capacitor. note 8: the switch connecting the reference buffer to ain_/ref has a typical on-resistance of 675 . note 9: adc performance is limited by the converter? noise floor, typically 1.4mv p-p . note 10: electrical characteristics are guaranteed from v dd(min) to v dd(max) . for operation beyond this range, see the typical operating characteristics . note 11: power-supply rejection ratio is measured as: , for the max1037/max1039 where n is the number of bits and v ref = 2.048v. power-supply rejection ratio is measured as: , for the max1036/max1038 where n is the number of bits and v ref = 4.096v. note 12: a master device must provide a data hold time for sda (referred to v il of scl) in order to bridge the undefined region of scl? falling edge (figure 1). note 13: c b = total capacitance of one bus line in pf. t r , t fda , and t f measured between 0.3v dd and 0.7v dd . the minimum value is specified at +25? with c b = 400pf. note 14: f sclh must meet the minimum clock low time plus the rise/fall times. vvvv v vv fs fs n ref 55 45 2 55 45 .. .. () ? () [] ? vvvv v vv fs fs n ref 33 27 2 33 27 .. .. () ? () [] ?
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 6 _______________________________________________________________________________________ typical operating characteristics (v dd = 3.3v (max1037/max1039), v dd = 5v (max1036/max1038), f scl = 1.7mhz, external clock (33% duty cycle), f sample = 188ksps, single ended, unipolar, t a = +25?, unless otherwise noted.) 150 250 200 350 300 400 450 supply current vs. voltage max1036 toc01 v dd (v) i dd ( a) 2.5 3.5 4.0 3.0 4.5 5.0 5.5 a) internal 4.096v ref b) internal 2.048v ref c) external 4.096v ref d) external 2.048v ref a c b d 150 250 200 350 300 400 450 -40 85 supply current vs. temperature max1036 toc02 temperature ( c) i dd ( a) 10 -15 35 60 internal 4.096v ref internal 2.048v ref external 4.096v ref external 2.048v ref 0 1 3 2 4 5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 shutdown supply current vs. supply voltage max1036 toc03 v dd (v) i dd ( a) sda = scl = v dd 0 1 3 2 4 5 -40 10 -15 35 60 85 shutdown supply current vs. temperature max1036 toc04 temperature ( c) i dd ( a) sda = scl = v dd v dd = 5v v dd = 3.3v 0 100 50 200 150 300 250 350 02030 10 40 50 60 average supply current vs. conversion rate (internal clock) max1036 toc05 conversion rate (ksps) average i dd ( a) a) internal ref always on b) internal ref autoshutdown c) external ref a c b internal clock mode f scl = 1.7mhz 0 150 100 50 300 250 200 450 400 350 500 0100 50 150 200 average supply current vs. conversion rate (external clock) max1036 toc06 conversion rate (ksps) average i dd ( a) a c b a) internal ref always on b) internal ref autoshutdown c) external ref external clock mode f scl = 1.7mhz 0.9900 0.9925 0.9950 0.9975 1.0000 1.0025 1.0050 1.0075 1.0100 4.00 4.50 4.25 4.75 5.00 5.25 5.50 normalized 4.096v reference voltage vs. supply voltage max1036 toc7 v dd (v) v ref normalized 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 -40 -15 10 35 60 85 internal 4.096v reference voltage vs. temperature max1036 toc08 temperature ( c) v ref normalized 0.9900 0.9925 0.9950 0.9975 1.0000 1.0025 1.0050 1.0075 1.0100 2.5 3.5 3.0 4.0 4.5 5.0 5.5 internal 2.048v reference voltage vs. supply voltage max1036 toc09 v dd (v) v ref normalized
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs _______________________________________________________________________________________ 7 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 -40 -15 10 35 60 85 internal 2.048v reference voltage vs. temperature max1036 toc10 temperature ( c) v ref normalized -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 100 50 150 200 250 300 differential nonlinearity vs. digital code max1036 toc11 digital output code dnl (lsb) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 100 50 150 200 250 300 integral nonlinearity vs. digital code max1036 toc12 digital output code inl (lsb) -120 -80 -100 -40 -60 -20 0 0 100k fft plot max1036 toc13 frequency (hz) amplitude (dbc) 40k 20k 60k 80k f sample = 188ksps f in = 25khz 0 0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.5 3.5 3.0 4.0 4.5 5.0 5.5 offset error vs. supply voltage max1036 toc14 v dd (v) offset error (lsb) v ref = 2.048v 0 0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -40 10 -15 356085 offset error vs. temperature max1036 toc15 temperature ( c) offset error (lsb) v dd = 3.3v v ref = 2.048v -0.1 -0.07 -0.08 -0.09 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 2.5 3.5 3.0 4.0 4.5 5.0 5.5 gain error vs. supply voltage max1036 toc16 v dd (v) gain error (lsb) v ref = 2.048v typical operating characteristics (continued) (v dd = 3.3v (max1037/max1039), v dd = 5v (max1036/max1038), f scl = 1.7mhz, external clock (33% duty cycle), f sample = 188ksps, single ended, unipolar, t a = +25?, unless otherwise noted.)
max1036?ax1039 detailed description the max1036?ax1039 adcs use successive- approximation conversion techniques and input t/h cir- cuitry to capture and convert an analog signal to a serial 8-bit digital output. the max1036/max1037 are 4-channel adcs, and the max1038/max1039 are 12- channel adcs. these devices feature a high-speed 2- wire serial interface supporting data rates up to 1.7mhz. figure 3 shows the simplified functional dia- gram for the max1038/max1039. power supply the max1036?ax1039 operate from a single supply and consume 350? at sampling rates up to 188ksps. the max1037/max1039 feature a 2.048v internal reference and the max1036/max1038 feature a 4.096v internal reference. all devices can be configured for use with an external reference from 1v to v dd . analog input and track/hold the max1036?ax1039 analog input architecture con- tains an analog input multiplexer (mux), a t/h capaci- tor, t/h switches, a comparator, and a switched capacitor digital-to-analog converter (dac) (figure 4). in single-ended mode, the analog input multiplexer con- nects c t/h to the analog input selected by cs[3:0] (see the configuration/setup bytes (write cycle) section). the charge on c t/h is referenced to gnd when converted. in pseudo-differential mode, the analog input multiplexer connects c t/h to the + analog input selected by cs[3:0]. the charge on c t/h is referenced to the ??ana- log input when converted. the max1036?ax1039 input configuration is pseudo- differential in that only the signal at the ??analog input is sampled with the t/h circuitry. the ??analog input signal must remain stable within ?.5lsb (?.1lsb for best results) with respect to gnd during a conversion. to accomplish this, connect a 0.1? capacitor from ? analog input to gnd. see the single-ended/pseudo- differential input section. during the acquisition interval, the t/h switches are in the track position and c t/h charges to the analog input signal. at the end of the acquisition interval, the t/h switches move to the hold position retaining the charge on c t/h as a sample of the input signal. during the conversion interval, the switched capacitive dac adjusts to restore the comparator input voltage to zero within the limits of 8-bit resolution. this action requires eight conversion clock cycles and is equiva- lent to transferring a charge of 18pf (v in + - v in -) from c t/h to the binary weighted capacitive dac form- ing a digital representation of the analog input signal. sufficiently low source impedance is required to ensure an accurate sample. a source impedance below 1.5k does not significantly degrade sampling accuracy. to minimize sampling errors with higher source imped- ances, connect a 100pf capacitor from the analog input to gnd. this input capacitor forms an rc filter with the source impedance limiting the analog input bandwidth. for larger source impedances, use a buffer amplifier to maintain analog input signal integrity. when operating in internal clock mode, the t/h circuitry enters its tracking mode on the ninth falling clock edge 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 8 _______________________________________________________________________________________ pin max1036/ max1037 max1038/ max1039 name function 1, 2, 3 8, 7, 6 ain0?in2 5, 4, 3, 2, 1 ain3?in7 16, 15, 14 ain8?in10 analog inputs 4 ain3/ref analog input 3/reference input or output. selected in the setup register. 13 ain11/ref analog input 11/reference input or output. selected in the setup register. 5 9 scl clock input 6 10 sda data input/output 7 11 gnd ground 812v dd positive supply. bypass to gnd with a 0.1? capacitor. pin description
of the address byte (see the slave address section). the t/h circuitry enters hold mode two internal clock cycles later. a conversion or series of conversions are then internally clocked (eight clock cycles per conver- sion) and the max1036?ax1039 hold scl low. when operating in external clock mode, the t/h circuitry enters track mode on the seventh falling edge of a valid slave address byte. hold mode is then entered on the falling edge of the eighth clock cycle. the conversion is performed during the next eight clock cycles. the time required for the t/h circuitry to acquire an input signal is a function of input capacitance. if the analog input source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the minimum time needed for the signal to be acquired. it is calculated by: t acq 6.25 (r source + r in ) c in where r source is the analog input source impedance, r in = 2.5k , and c in = 18pf. t acq is 1/f scl for external clock mode. for internal clock mode, the acquisition time is two internal clock cycles. to select r source , allow 625ns for t acq in internal clock mode to account for clock frequency variations. max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs _______________________________________________________________________________________ 9 t hd.sta t su.dat t high t r t f t hd.dat t hd.sta s sr a scl sda t su.sta t low t buf t su.sto ps t hd.sta t su.dat t high t fcl t hd.dat t hd.sta s sr a scl sda t su.sta t low t buf t su.sto s t rcl t rcl1 hs-mode f/s-mode a. f/s-mode i 2 c serial interface timing b. hs-mode i 2 c serial interface timing t fda t rda t t r t f figure 1. i 2 c serial interface timing v dd i ol = 3ma i oh = 0ma v out 400pf sda figure 2. load circuit
max1036?ax1039 analog input bandwidth the max1036?ax1039 feature input tracking circuitry with a 2mhz small signal-bandwidth. the 2mhz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and protection internal protection diodes clamp the analog input to v dd and gnd. these diodes allow the analog inputs to swing from (gnd - 0.3v) to (v dd + 0.3v) without caus- ing damage to the device. for accurate conversions, the inputs must not go more than 50mv below gnd or above v dd . if the analog input exceeds v dd by more than 50mv, the input current should be limited to 2ma. 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 10 ______________________________________________________________________________________ analog input mux ain1 ain11/ref ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain0 scl sda input shift register setup register configuration register control logic reference 4.096v (max1038) 2.048v (max1039) internal oscillator output shift register and 12-byte ram ref t/h 8-bit adc v dd gnd max1038 max1039 figure 3. max1038/max1039 simplified functional diagram track hold c t/h track hold differential single ended ain0 ain1 ain2 ain3/ref gnd analog input mux capacitive dac ref max1036 max1037 figure 4. equivalent input circuit
single-ended/pseudo-differential input the sgl/ dif bit of the configuration byte configures the max1036?ax1039 analog input circuitry for single- ended or pseudo-differential inputs (table 2). in single- ended mode (sgl/ dif = 1), the digital conversion results are the difference between the analog input selected by cs[3:0] and gnd (table 3). in pseudo-differential mode (sgl/ dif = 0), the digital conversion results are the differ- ence between the ??and the ??analog inputs selected by cs[3:0] (table 4). the ??analog input signal must remain stable within ?.5lsb (?.1lsb for best results) with respect to gnd during a conversion. unipolar/bipolar when operating in pseudo-differential mode, the bip/ uni bit of the setup byte (table 1) selects unipolar or bipolar operation. unipolar mode sets the differential analog input range from zero to v ref . a negative differ- ential analog input in unipolar mode causes the digital output code to be zero. selecting bipolar mode sets the differential input range to ? ref /2, with respect to the negative input. the digital output code is binary in unipolar mode and two? complement binary in bipolar mode (see the transfer functions section). in single-ended mode, the max1036?ax1039 always operate in unipolar mode regardless of the bip/ uni setting, and the analog inputs are internally referenced to gnd with a full-scale input range from zero to v ref . digital interface the max1036?ax1039 feature a 2-wire interface con- sisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communica- tion between the max1036?ax1039 and the master at rates up to 1.7mhz. the max1036?ax1039 are slaves that transmit and receive data. the master (typi- cally a microcontroller) initiates data transfer on the bus and generates scl to permit that transfer. sda and scl must be pulled high. this is typically done with pullup resistors (500 or greater) (see typical operating circuit ). series resistors (r s ) are optional. they protect the input architecture of the max1036?ax1039 from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl clock cycle. nine clock cycles are required to transfer the data in or out of the max1036?ax1039. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). both sda and scl idle high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi- tion (s), a high-to-low transition on sda with scl high. the master terminates a transmission with a stop condition (p), a low-to-high transition on sda, while max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ______________________________________________________________________________________ 11 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg sel2 sel1 sel0 clk bip/ uni rst x bit name description 7 reg register bit. 1 = setup byte, 0 = configuration byte (table 2). 6 sel2 5 sel1 4 sel0 three bits select the reference voltage and the state of ain_/ref (table 6). default to 000 at power-up. 3 clk 1 = external clock, 0 = internal clock. defaulted to zero at power-up. 2 bip/ uni 1 = bipolar, 0 = unipolar. defaulted to zero at power-up (see the unipolar/bipolar section). 1 rst 1 = no action, 0 = resets the configuration register to default. setup register remains unchanged. 0 x don? care, can be set to 1 or 0. table 1. setup byte format
max1036?ax1039 scl is high (figure 5). a repeated start condition (sr) can be used in place of a stop condition to leave the bus active and in its current timing mode (see the hs- mode section). acknowledge bits successful data transfers are acknowledged with an acknowledge bit (a) or a not-acknowledge bit ( a ). both the master and the max1036?ax1039 (slave) generate acknowledge bits. to generate an ?cknowledge,?the receiving device must pull sda low before the rising edge of the acknowledge related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 6). to generate a ?ot acknowledge,?the receiver allows sda to be pulled high before the rising edge of the acknowledge related clock pulse and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the bus master should reattempt communication at a later time. slave address a bus master initiates communication with a slave device by issuing a start condition followed by a slave address. when idle, the max1036?ax1039 con- tinuously wait for a start condition followed by their slave address. when the max1036?ax1039 recog- nize their slave address, they are ready to accept or send data. the slave address has been factory pro- grammed and is always 1100100 for the max1036/ max1037, and 1100101 for max1038/ max1039 (figure 7). the least significant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from the max1036?ax1039 (r/ w = zero selects a write condition. r/ w = 1 selects a read condi- tion). after receiving the address, the max1036 max1039 (slave) issue an acknowledge by pulling sda low for one clock cycle. bus timing at power-up, the max1036?ax1039 bus timing defaults to fast mode (f/s-mode) allowing conversion rates up to 44ksps. the max1036?ax1039 must operate in high-speed mode (hs-mode) to achieve conversion rates up to 188ksps. figure 1 shows the bus timing for the max1036?ax1039? 2-wire interface. hs-mode at power-up, the max1036?ax1039 bus timing is set for f/s-mode. the master selects hs-mode by address- ing all devices on the bus with the hs-mode master code 0000 1xxx (x = don? care). after successfully receiving the hs-mode master code, the max1036 max1039 issues a not acknowledge, allowing sda to be pulled high for one clock cycle (figure 8). after the not acknowledge, the max1036?ax1039 are in hs-mode. the master must then send a repeated start followed by a slave address to initiate hs-mode communication. if the master generates a stop condition, the max1036?ax1039 return to f/s-mode. configuration/setup bytes (write cycle) write cycles begin with the master issuing a start condition followed by 7 address bits (figure 7) and 1 write bit (r/ w = zero). if the address byte is successful- ly received, the max1036?ax1039 (slave) issue an acknowledge. the master then writes to the slave. the slave recognizes the received byte as the setup byte (table 1) if the most significant bit (msb) is 1. if the msb is zero, the slave recognizes that byte as the con- figuration byte (table 2). the master can write either 1 or 2 bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte only; configuration byte only; figure 9). if the slave receives bytes successfully, it issues an acknowl- edge. the master ends the write cycle by issuing a stop condition or a repeated start condition. when operating in hs-mode, a stop condition returns the bus to f/s-mode (see the hs-mode section). data byte (read cycle) a read cycle must be initiated to obtain conversion results. read cycles begin with the bus master issuing 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 12 ______________________________________________________________________________________ scl sda sp sr figure 5. start and stop conditions scl sda s not acknowledge acknowledge 12 89 figure 6. acknowledge bits
a start condition followed by 7 address bits and a read bit (r/ w = 1). if the address byte is successfully received, the max1036?ax1039 (slave) issue an acknowledge. the master then reads from the slave. after the master has received the results, it can issue an acknowledge if it wants to continue reading or a not acknowledge if it no longer wishes to read. if the max1036?ax1039 receive a not acknowledge, they release sda allowing the master to generate a stop or repeated start. see the clock mode and scan mode sections for detailed information on how data is obtained and converted. clock mode the clock mode determines the conversion clock, the acquisition time, and the conversion time. the clock mode also affects the scan mode. the state of the setup byte? clk bit determines the clock mode (table 1). at power-up, the max1036?ax1039 default to internal clock mode (clk = zero). internal clock when configured for internal clock mode (clk = zero), the max1036?ax1039 use their internal oscillator as the conversion clock. in internal clock mode, the max1036?ax1039 begin tracking analog input on the ninth falling clock edge of a valid slave address byte. two internal clock cycles later, the analog signal is acquired and the conversion begins. while tracking and converting the analog input signal, the max1036?ax1039 hold scl low (clock stretching). after the conversion completes, the results are stored max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ______________________________________________________________________________________ 13 110 1 000r/w a slave address s scl sda 123456789 device slave address 1100100 1100101 max1036/max1037 max1038/max1039 figure 7. max1036/max1037 slave address byte 000 1 0xxx a hs-mode master code scl sda s sr f/s-mode hs-mode figure 8. f/s-mode to hs-mode transfer
max1036?ax1039 in random access memory (ram). if the scan mode is set for multiple conversions, they all happen in succes- sion with each additional result being stored in ram. the max1036/max1037 contain 8 bytes of ram, and the max1038/max1039 contain 12 bytes of ram. once all conversions are complete, the max1036?ax1039 release scl, allowing it to be pulled high. the master can now clock the results out of the output shift register at a clock rate of up to 1.7mhz. scl is stretched for a maximum acquisition and conversion time of 7.6? per channel (figure 10). the device ram contains all of the conversion results when the max1036?ax1039 release scl. the con- verted results are read back in a first-in-first-out (fifo) sequence. if ain_/ref is set to be a reference input or output (sel1 = 1, table 6), ain_/ref is excluded from a multichannel scan. ram contents can be read contin- uously. if reading continues past the last result stored in ram, the pointer wraps around and points to the first result. note that only the current conversion results are read from memory. the device must be addressed with a read command to obtain new conversion results. the internal clock mode? clock stretching quiets the scl bus signal, reducing the system noise during con- version. using the internal clock also frees the master (typically a microcontroller) from the burden of running the conversion clock. external clock when configured for external clock mode (clk = 1), the max1036?ax1039 use scl as the conversion clock. in external clock mode, the max1036?ax1039 begin tracking the analog input on the seventh falling clock edge of a valid slave address byte. one scl clock cycle later, the analog signal is acquired and the conversion begins. unlike internal clock mode, convert- ed data is available immediately after the slave-address acknowledge bit. the device continuously converts input channels dictated by the scan mode until given a not acknowledge. there is no need to readdress the device with a read command to obtain new conversion results (figure 11). the conversion must complete in 9ms or droop on the t/h capacitor degrades conversion results. use internal clock mode if the scl clock period exceeds 1ms. the max1036?ax1039 must operate in external clock mode for conversion rates up to 188ksps. scan mode scan0 and scan1 of the configuration byte set the scan mode configuration. table 5 shows the scanning configurations. if ain_/ref is set to be a reference input or output (sel1 = 1, table 6), ain_/ref is excluded from a multichannel scan. 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 14 ______________________________________________________________________________________ b. 2-byte write cycle slave to master master to slave s 1 slave address a 711 w setup or configuration byte setup or configuration byte 8 p or sr 1 a 1 msb determines whether setup or configuration byte s 1 slave address a 711 w setup or configuration byte 8 p or sr 1 a 1 msb determines whether setup or configuration byte a 1 8 a. 1-byte write cycle number of bits number of bits figure 9. write cycle
max1036?ax1039 applications information power-on reset the configuration and setup registers (tables 1 and 2) default to a single-ended, unipolar, single-channel con- version on ain0 using the internal clock with v dd as the reference and ain_/ref configured as an analog input. the ram contents are unknown after power-up. automatic shutdown sel[2:0] of the setup byte (tables 1 and 6) controls the state of the reference and ain_/ref. if automatic shut- down is selected (sel[2:0] = 100), shutdown occurs between conversions when the max1036?ax1039 are idle. when operating in external clock mode, a stop condition must be issued to place the devices in idle mode and benefit from automatic shutdown. a stop condition is not necessary in internal clock mode to ben- efit from automatic shutdown because power-down occurs once all contents are written to memory (figure 10). all analog circuitry is inactive in shutdown and sup- ply current is less than 1?. the digital conversion results are maintained in ram during shutdown and are available for access through the serial interface at any time prior to a stop or repeated start condition. when idle, the max1036?ax1039 wait for a start condition followed by their slave address (see the slave address section). upon reading a valid address byte, the max1036?ax1039 power up. the analog circuits do not require any wakeup time from shutdown, whether using external or internal reference. automatic shutdown results in dramatic power savings, particularly at slow conversion rates. for example, at a conversion rate of 10ksps, the average supply current for the max1036 is 8? and drops to 2? at 1ksps. at 0.1ksps the average supply current is just 1? (see average supply current vs. conversion rate in the typical operating characteristics section). reference voltage sel[2:0] of the setup byte (table 1) controls the refer- ence and the ain_/ref configuration (table 6). when ain_/ref is configured to be a reference input or refer- ence output (sel1 = 1), conversions on ain_/ref appear as if ain_/ref is connected to gnd (see note 2 of tables 3 and 4). internal reference the internal reference is 4.096v for the max1036/ max1038 and 2.048v for the max1037/max1039. sel1 of the setup byte controls whether ain_/ref is used for an analog input or a reference (table 6). when ain_/ref is configured to be an internal reference out- put (sel[2:1] = 11), decouple ain_/ref to gnd with a 0.01? capacitor. due to the decoupling capacitor and the 675 reference source impedance, allow 80? for the reference to stabilize during initial power-up. once powered up, the reference always remains on until reconfigured. the reference should not be used to sup- ply current for external circuitry. 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ______________________________________________________________________________________ 15 bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg scan1 scan0 cs3 cs2 cs1 cs0 sgl/ dif bit name description 7 reg register bit. 1 = setup byte (table 1), 0 = configuration byte. 6 scan1 5 scan0 scan select bits. two bits select the scanning configuration (table 5). default to 00 at power-up. 4 cs3 3 cs2 2 cs1 1 cs0 channel select bits. four bits select which analog input channels are to be used for conversion (tables 3, 4). default to 0000 at power-up. for max1036/max1037, cs3 and cs2 are internally set to 0. 0 sgl/ dif 1 = single-ended, 0 = pseudo-differential (tables 3, 4). default to 1 at power-up (see the single- ended/pseudo-differential input section). table 2. configuration byte format
b. scan mode conversions with internal clock note: t acq + t conv 7.6 s per channel. s 1 slave address a 711 r clock stretch number of bits p or sr 1 8 result a 1 a. single conversion with internal clock s 1 slave address 711 r clock stretch a number of bits p or sr 1 8 result 1 a 1 a 8 result 2 a 8 result n slave to master master to slave t conv1 clock stretch t acq1 t conv2 t acq2 t convn t acqn t conv t acq 1 1 figure 10. internal clock mode read cycles slave address result 1 result 2 result n t conv1 t acq1 t conv2 t acq2 t convn t acqn t conv t acq number of bits number of bits 1 8 a 1 s 1 a 711 r s 1 a 711 r p or sr 1 8 a 1 a 8 a 8 b. scan mode conversions with external clock 1 1 slave address p or sr result a. single conversion with external clock slave to master master to slave figure 11. external clock mode read cycles max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 16 ______________________________________________________________________________________
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ______________________________________________________________________________________ 17 cs3 1 cs2 1 cs1 cs0 ain0 ain1 ain2 ain3 2 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 2 gn d 0000+ - 0001 + - 0010 + - 0011 + - 0100 + - 0101 + - 0110 + - 0111 + - 1000 + - 1001 +- 1010 +- 1011 +- 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved table 3. channel selection in single-ended mode (sgl / dif = 1) note 1: for max1036/max1037, cs3 and cs2 are internally set to zero. note 2: when sel1 = 1, a single-ended read of ain3/ref (max1036/max1037) or ain11/ref (max1038/max1039) returns gnd.
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 18 ______________________________________________________________________________________ cs3 1 cs2 1 cs1 cs0 ain0 ain1 ain2 ain3 2 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 2 0000+- 0001 -+ 0010 +- 0011 -+ 0100 +- 0101 -+ 0110 +- 0111 -+ 1000 +- 1001 -+ 1010 +- 1011 -+ 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved table 4. channel selection in pseudo-differential mode (sgl / dif = 0) note 1: for max1036/max1037, cs3 and cs2 are internally set to zero. note 2: when sel1 =1, a pseudo-differential read between ain2 and ain3/ref (max1036/max1037) or ain10 and ain11/ref (max1038/max1039) returns the difference between gnd and ain2 or ain10, respectively. for example, a pseudo-differen- tial read of 1011 returns the negative difference between ain10 and gnd. note 3: when scanning multiple channels (scan0 = 0), cs0 = 0 causes the even-numbered channel-select bits to be scanned, while cs0 = 1 causes the odd-numbered channel-select bits to be scanned. for example, if the max1038/max1039 scan[1:0] = 00 and cs[3:0] = 1010, a pseudo-differential read returns ain0?in1, ain2?in3, ain4?in5, ain6?in7, ain8?in9, and ain10?in11. if the max1038/max1039 scan[1:0] = 00 and cs[3:0] = 1011, a pseudo-differential read returns ain1?in0, ain3?in2, ain5?in4, ain7?in6, ain9?in8, and ain11?in10.
max1036?ax1039 external reference the external reference can range from 1.0v to v dd . for maximum conversion accuracy, the reference must be able to deliver up to 30? and have an output imped- ance of 1k or less. if the reference has a higher output impedance or is noisy, bypass it to gnd as close to ain_/ref as possible with a 0.1? capacitor. transfer functions output data coding for the max1036?ax1039 is binary in unipolar mode and two? complement binary in bipolar mode with 1lsb = (v ref /2 n ) where n is the number of bits (8). code transitions occur halfway between succes- sive-integer lsb values. figures 12 and 13 show the input/output (i/o) transfer functions for unipolar and bi- polar operations, respectively. layout, grounding, and bypassing for best performance, use pc boards. wire-wrap config- urations are not recommended since the layout should ensure proper separation of analog and digital traces. do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the adc package. use separate analog and digital pc board ground sections with only one star point (figure 14) con- necting the two ground systems (analog and digital). for lowest noise operation, ensure the ground return to the star ground? power supply is low impedance and as short as possible. route digital signals far away from sen- sitive analog and reference inputs. high-frequency noise in the power supply (v dd ) could influence the proper operation of the adc? fast comparator. bypass v dd to the star ground with a 0.1? capacitor located as close as possible to the max1036?ax1039 power-supply pin. minimize capacitor lead length for best supply-noise rejection, and add an attenuation resistor (5 ) if the power sup- ply is extremely noisy. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the inl is measured using the endpoint method. scan1 scan0 scanning configuration 0 0 scans up from ain0 to the input selected by cs3?s0 (default setting). 0 1 converts the input selected by cs3?s0 eight times.* scans up from ain2 to the input selected by cs1 and cs0. when cs1 and cs0 are set for ain0?in2, the scanning stops at ain2 (max1036/max1037). 10 scans up from ain6 to the input selected by cs3?s0. when cs3?s0 is set for ain0?in6 scanning stops at ain6 (max1038/max1039). 1 1 converts the channel selected by cs3?s0.* table 5. scanning configuration * when operating in external clock mode, there is no difference between scan[1:0] = 01 and scan[1:0] = 11 and converting continue s until a not acknowledge occurs. sel2 sel1 sel0 reference voltage ain_/ref internal reference state 00xv dd analog input always off 0 1 x external reference reference input always off 1 0 0 internal reference analog input auto shutdown 1 0 1 internal reference analog input always on 1 1 x internal reference reference output always on table 6. reference voltage and ain_/ref format x = don? care. 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ______________________________________________________________________________________ 19
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 20 ______________________________________________________________________________________ differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital sam- ples, signal-to-noise ratio (snr) is the ratio of full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 n + 1.76)db input voltage (lsb) output code 1...111 1...110 1...101 1...100 0...000 0...001 0...010 0...011 23 256 v ref 1lsb = 1 253 255 254 ref 256 0 252 figure 12. unipolar transfer function input voltage (lsb) output code (two's complement) 0...111 0...110 0...101 0...100 1...000 1...001 1...010 1...011 -1 -126 -125 256 v ref 1lsb = 0+1 -127 +125 +127 +126 0...000 0...001 1...111 ref +128 -128 +124 '-' input figure 13. bipolar transfer function 3v/5v v logic = 3v/5v gnd supplies dgnd 3v/5v gnd 0.1 f v dd digital circuitry max1036 max1037 max1038 max1039 r* = 5 *optional figure 14. power-supply and grounding connections
in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to rms equivalent of all other adc output signals. sinad (db) = 20 log (signal rms / noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the adc? full-scale range, calculate the enob as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the input signal? first five harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component. thd v v v v v = +++ ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log / max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs ______________________________________________________________________________________ 21 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code document no. 8 sot23 k8cn+2 21-0078 16 qsop e16+4 21-0055 chip information process: bicmos
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs 22 ______________________________________________________________________________________ sda scl ain3/ref 1 2 8 7 v dd gnd ain1 ain2 ain0 sot23 top view 3 4 6 5 max1036 max1037 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ain7 ain8 ain9 ain10 ain11/ref v dd gnd sda scl max1038 max1039 qsop ain6 ain5 ain2 ain4 ain3 ain1 ain0 pin configurations *optional *r s *r s analog inputs c sda scl gnd v dd sda scl ain0 ain1 ain2 ain3/ref 5v 5v r p r p 5v max1036 max1037 max1038 max1039 typical operating circuit
max1036?ax1039 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel 2-wire serial 8-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 23 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 2 5/08 updated ordering information table 1, 21 3 2/09 discontinued some versions of the family 1, 5, 18, 21 4 5/09 updated note 13 in electrical characteristics table 5

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